An EEPROM or electrically erasable programmable read-only memory is a non-volatile storage unit used in computers or other devices. An EEPROM can be programmed and erased electrically multiple times. Each bit is set by quantum tunneling electrons across a thin dielectric barrier. Because of this it may be erased and reprogrammed only a certain number of times, but an EEPROM can be read for an unlimited number of times.
EEPROM memory cells may comprise different kinds of memory cells, for example a floating gate cell or a so-called nitride programmable read-only memory (NROM) cell. The NROM cell is described in U.S. Pat. No. 6,011,725, which is incorporated herein by reference.
The NROM cell has two doping areas and a channel that is located between the doping areas. A gate electrode is arranged above the channel region insulated by a dielectric layer that is arranged between the channel region and the gate electrode. The dielectric layer includes an oxide-nitride-oxide layer comprising a nitride layer serving as a charge-trapping layer sandwiched between the insulating oxide layers, which avoid vertical retention. Two bits are stored in physically different regions of the nitride layer. A first bit region is located near the first doping area and a second bit region is located near the second doping area.
The bits are programmed by means of channel hot electron programming. Electrons may be injected from the channel into the charge-trapping region according to applied voltages. Programming of a first bit may be performed by applying a programming voltage to the first doping area and the gate while grounding the second doping area. The electrons are injected and trapped in the first bit region. Likewise programming of a second bit may be performed by applying the programming voltage to the second doping area in the gate while grounding the first doping area. For erasing a bit, hot holes or Fowler-Nordheim tunneling can be used. Erasing of the first bit may be performed by applying erasing voltages to the gate or to the first doping area and the gate resulting in a lateral field. Holes are caused to flow through the bottom oxide layer for compensating the charge of the electrons.
The step of applying programming or erasing voltages is performed by applying a sequence of several pulses. The number of pulses that are needed to program or erase the memory cell may differ from cell to cell. Nevertheless, the number of pulses increases with the number of programming or erasing cycles that have already been performed. Programming and erasing a memory cell is a general concept that is not limited to NROM cells.
A bit information stored in the NROM cell is read by applying a reverse voltage between the first and second doping areas compared to the programming voltage that is used to program the bit. Relatively small charges near the grounded one of the first or second doping area prevent or reduce current flow, for example reading of the first bit may be performed by applying reading voltages to the second doping area and the gate. The first doping area may be grounded. The current flows while there are no trapped charges inside the first bit region. While there are trapped charges or electrons inside the first bit region the current flow is reduced or the current does not flow. Reduced current flow represents a first binary value of the programmed bit and normal current flow represents a second binary value of the bit.
In order to perform memory access to the memory cells, the memory device further comprises a controller that is coupled to the memory cell array and executes memory access to the memory cells. Normally the memory cell array is organized in blocks. Each of the memory cells is assigned to one of the blocks. The memory access may be performed block wise. This means that a group of bits is preferably programmed in the same block. Furthermore, the memory cells assigned to the same block may be erased synchronistically.
The memory device is generally tested for functionality by the manufacturer before delivery. Blocks that comprise at least one defect memory cell may be marked as so-called bad blocks or replaced with redundant blocks. The controller does not execute memory access to these bad blocks. Testing may comprise performing memory access to each memory cell by applying an access signal in order to program or erase the memory cells. The access signal may comprise several pulses. The number of pulses needed to perform access, by programming or erasing, to the memory cell is determined during the testing routine. If the memory cell cannot be accessed by a given number of pulses it is assumed that the memory cell is defective. Consequently, the block including the defective memory cell is marked as a bad block.
During normal operation mode of the memory device, programming and erasing of the memory cells is performed many times. Due to deterioration of the memory cells, blocks that are programmed and erased more often than other blocks wear much faster. The lifetime of a block may be defined by a given number of programming or erasing cycles that can be performed to the memory cells of the block. After having performed the given number of programming or erasing cycles, the memory cells possibly become defective because of their limited lifetime. The block may be marked as a bad block resulting in not using it any more. Consequently, the storage capacity of the memory device decreases block wise during its lifetime if more and more blocks are marked as bad blocks.
The controller may perform memory access using so-called wear leveling. Wear leveling is a technique in order to spread wear caused by repeated programming or erasing evenly across the memory cell array and thus avoid wearing out specific blocks of the memory cell array. The wear leveling technique can be done by the controller. The controller selects the block for executing memory access based upon the number of writing or erasing cycles that have been performed so far. After having reached the given number of writing or erasing cycles the block is marked as a bad block.
Marking does not depend on the real state of the block but only on the number of writing or erasing cycles. Consequently, if the given number that defines the lifetime of the block is underestimated, the block is marked as a bad block although it still functions. Sometimes memory access is still executed to a block that has become defective although the given number of writing or erasing cycles has not been reached. The lifetime of a block is defined merely by a given number of writing or erasing cycles, not considering the real state of the memory cells of the block. Consequently, the defined lifetime of the block is based on an underestimation of the real lifetime of the memory cells.